View MAX5099_200885.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

19-4112; Rev 0; 5/08
KIT ATION EVALU ILABLE AVA
Dual, 2.2MHz, Automotive Synchronous Buck Converter with 80V Load-Dump Protection
General Description
The MAX5099 offers a dual-output, high-switching-frequency DC-DC buck converter with an integrated highside switch. The MAX5099 integrates two low-side MOSFET drivers to allow each converter to drive an external synchronous-rectifier MOSFET. Converter 1 delivers up to 2A output current, and converter 2 can deliver up to 1A of output current. The MAX5099 integrates load-dump protection circuitry that is capable of handling load-dump transients up to 80V for automotive applications. The load-dump protection circuit utilizes an internal charge pump to drive the gate of an external n-channel MOSFET. When an overvoltage or loaddump condition occurs, the series protection MOSFET absorbs the high voltage transient to prevent damage to lower voltage components. The DC-DC converter operates over a wide 4.5V to 19V operating voltage range. The MAX5099 operates 180 out-of-phase with an adjustable switching frequency to minimize external components while allowing the ability to make trade-offs between the size, efficiency, and cost. The high switching frequency also allows these devices to operate outside the AM band for automotive applications. These regulators can be protected against high voltage transients such as a load-dump condition by using the integrated overvoltage controller. This device utilizes voltage-mode control for stable operation and external compensation, so that the loop gain is tailored to optimize component selection and transient response. The MAX5099 has a maximum duty cycle of 92.5% and is synchronized to an external clock fed at the SYNC input. Additional features include internal digital soft-start, individual enable for each DC-DC regulator (EN1 and EN2), open-drain power-good outputs (PGOOD1 and PGOOD2), and shutdown input (ON/OFF). Other features of the MAX5099 include overvoltage protection and short-circuit (hiccup current limit) and thermal protection. The MAX5099 is available in a thermally enhanced, exposed pad 5mm x 5mm, 32-pin TQFN package and operates over the automotive -40C to +125C temperature range.
Features
Wide 4.5V to 5.5V or 5.2V to 19V Input Voltage Range with 80V Load-Dump Protection Dual-Output DC-DC Converter with Integrated Power MOSFETs Adjustable Outputs from 0.8V to 0.9VIN Output Current Capability Up to 2A and 1A Switching Frequency Programmable from 200kHz to 2.2MHz Synchronization Input (SYNC) Individual Converter Enable Input and PowerGood Output Low-IQ (7A) Standby Current (ON/OFF) Internal Digital Soft-Start and Soft-Stop Short-Circuit Protection on Outputs and Maximum Duty-Cycle Limit Overvoltage Protection on Outputs with Auto Restart Thermal Shutdown Thermally Enhanced 32-Pin TQFN Package Dissipates Up to 2.7W at +70C
MAX5099
Ordering Information
PART MAX5099ATJ+ TEMP RANGE -40C to +125C PIN-PACKAGE 32 TQFN-EP*
+Denotes a lead-free package. *EP = Exposed pad.
Applications
Automotive AM/FM Radio Power Supply Automotive Instrument Cluster Display
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Dual, 2.2MHz, Automotive Synchronous Buck Converter with 80V Load-Dump Protection MAX5099
ABSOLUTE MAXIMUM RATINGS
V+ to SGND............................................................-0.3V to +25V V+ to IN_HIGH...........................................................-19V to +6V IN_HIGH to SGND ..................................................-0.3V to +19V IN_HIGH Maximum Input Current .......................................60mA BYPASS to SGND..................................................-0.3V to +2.5V GATE to V+.............................................................-0.3V to +12V GATE to SGND .......................................................-0.3V to +36V SGND to PGND .....................................................-0.3V to +0.3V VL to SGND ..................-0.3V to the Lower of +6V or (V+ + 0.3V) VDRV to SGND .........................................................-0.3V to +6V BST1/VDD1, BST2/VDD2, DRAIN_, PGOOD_ to SGND ..............................................-0.3V to +30V ON/OFF to SGND ...............................-0.3V to (IN_HIGH + 0.3V) BST1/VDD1 to SOURCE1, BST2/VDD2 to SOURCE2......................................-0.3V to +6V SOURCE_ to SGND................................................-0.6V to +25V EN_ to SGND............................................................-0.3V to +6V OSC, FSEL_1, COMP_, SYNC, FB_ to SGND..............................................-0.3V to (VL + 0.3V) DL_ to PGND ...........................................-0.3V to (VDRV + 0.3V) SOURCE1, DRAIN1 Peak Current ..............................5A for 1ms SOURCE2, DRAIN2 Peak Current ..............................3A for 1ms VL, BYPASS to SGND Short Circuit ................... Continuous, Internally Limited Continuous Power Dissipation (TA = +70C) 32-Pin TQFN-EP (derate 34.5mW/C above +70C)..2759mW Package Junction-to-Ambient Thermal Resistance (JA) (Note 1).............................29.0C/W Package Junction-to-Case Thermal Resistance (JC) (Note 1) ..............................1.7C/W Operating Temperature Range .........................-40C to +125C Storage Temperature Range ............................-65C to +150C Junction Temperature ......................................................+150C Lead Temperature (soldering, 10s) ................................+300C
Note 1: Package thermal resistances were obtained using the method described in JEDEC specifications. For detailed information on package thermal considerations refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDRV = VL, V+ = VL = IN_HIGH = 5.2V or V+ = IN_HIGH = 5.2V to 19V, EN_ = VL, SYNC = GND, IVL = 0mA, PGND = SGND, CBYPASS = 0.22F (low ESR), CVL = 4.7F (ceramic), CV+ = 1F (low ESR), CIN_HIGH = 1F (ceramic), RIN_HIGH = 3.9k, ROSC = 10k, TJ = -40C to +125C, unless otherwise noted.) (Note 2)
PARAMETER SYSTEM SPECIFICATIONS Input Voltage Range V+ Operating Supply Current V+ Standby Supply Current V+ IQ IV+STBY V+ = IN_HIGH VL = V+ = IN_HIGH, Figure 6 (Note 3) VL unloaded, no switching, VFB_ = 1V VEN_ = 0V, PGOOD_ unconnected, V+ = VIN_HIGH = 14V VOUT1 = 5V at 1.5A, VOUT2 = 3.3V at 0.75A, fSW = 300kHz ISINK = 10mA 1mA < ISINK < 50mA IIN_HIGH IIN_HIGHSTBY VOV VEN_ = VPGOOD_ = VGATE = 0V, VIN_HIGH = VON/OFF = 14V VON/OFF = 0V, VPGOOD_ = V+ = unconnected, VIN_HIGH = 14V VOV = V+ - VIN_HIGH, IGATE = -1mA 1.20 V+ = VL = 5.2V V+ = 12V V+ = 16V 19 5.2 4.5 4.2 0.75 86 85 85 20 160 270 7 1.85 600 9 2.50 21 V mV A A V % 19 5.5 6.0 1.1 V mA mA SYMBOL CONDITIONS MIN TYP MAX UNITS
Efficiency OVERVOLTAGE PROTECTOR IN_HIGH Clamp Voltage IN_HIGH Clamp Load Regulation IN_HIGH Supply Current IN_HIGH Standby Supply Current V+ to IN_HIGH Overvoltage Clamp
IN_HIGH
2
_______________________________________________________________________________________
Dual, 2.2MHz, Automotive Synchronous Buck Converter with 80V Load-Dump Protection
ELECTRICAL CHARACTERISTICS (continued)
(VDRV = VL, V+ = VL = IN_HIGH = 5.2V or V+ = IN_HIGH = 5.2V to 19V, EN_ = VL, SYNC = GND, IVL = 0mA, PGND = SGND, CBYPASS = 0.22F (low ESR), CVL = 4.7F (ceramic), CV+ = 1F (low ESR), CIN_HIGH = 1F (ceramic), RIN_HIGH = 3.9k, ROSC = 10k, TJ = -40C to +125C, unless otherwise noted.) (Note 2)
PARAMETER IN_HIGH Startup Voltage GATE Charge Current SYMBOL IN_HIGH UVLO IGATE_CH CONDITIONS Rising, ON/OFF = IN_HIGH, GATE rising Falling, ON/OFF = IN_HIGH, GATE falling VIN_HIGH = VON/OFF = 14V, VGATE = V+ = 0V V+ = VIN_HIGH = VON/OFF = 4.5V, IGATE = 1A V+ = VIN_HIGH = VON/OFF = 14V, IGATE = 1A VIN_HIGH = 14V, VON/OFF = 0V, V+ = 0V, VGATE = 5V 20 4.0 MIN TYP 3.6 3.45 45 5.3 9 3.6 mA 80 7.5 V MAX 4.1 UNITS V A
MAX5099
GATE Output Voltage
VGATE VIN_HIGH
GATE Turn-Off Pulldown Current STARTUP/VL REGULATOR VL Undervoltage-Lockout Trip Level VL Undervoltage-Lockout Hysteresis VL Output Voltage VL LDO Short-Circuit Current VL LDO Dropout Voltage BYPASS OUTPUT BYPASS Voltage BYPASS Load Regulation SOFT-START/SOFT-STOP Digital Ramp Period SoftStart/Soft-Stop Soft-Start/Soft-Stop Steps VOLTAGE-ERROR AMPLIFIER FB_ Input Bias Current FB_ Input-Voltage Set Point FB_ to COMP_ Transconductance INTERNAL MOSFETS On-Resistance High-Side MOSFET Converter 1
IGATE_PD
UVLO
VL falling
3.9
4.1 180
4.3
V mV
VL IVL_SHORT VLDO VBYPASS VBYPASS
ISOURCE_ = 0 to 40mA, 5.5V V+ 19V V+ = VIN_HIGH = 5.2V ISOURCE_ = 40mA, V+ = VIN_HIGH = 4.5V IBYPASS = 0A 0 < IBYPASS < 100A (sourcing)
5.0
5.2 130 300
5.5 550 2.02 5
V mA mV V mV
1.98
2.00 2
Internal 6-bit DAC
2048 64
fSW Clock Cycles Steps 250 nA V mS
IFB_ VFB_ gM -40C TA +85C -40C TA +125C 0.783 0.785 1.4 2.4 0.8
0.809 0.814 3.4
RON1
ISWITCH = 100mA, BST1/VDD1 to VSOURCE1 = 5.2V ISWITCH = 100mA, BST1/VDD1 to VSOURCE1 = 4.5V
195 m 208 355
_______________________________________________________________________________________
3
Dual, 2.2MHz, Automotive Synchronous Buck Converter with 80V Load-Dump Protection MAX5099
ELECTRICAL CHARACTERISTICS (continued)
(VDRV = VL, V+ = VL = IN_HIGH = 5.2V or V+ = IN_HIGH = 5.2V to 19V, EN_ = VL, SYNC = GND, IVL = 0mA, PGND = SGND, CBYPASS = 0.22F (low ESR), CVL = 4.7F (ceramic), CV+ = 1F (low ESR), CIN_HIGH = 1F (ceramic), RIN_HIGH = 3.9k, ROSC = 10k, TJ = -40C to +125C, unless otherwise noted.) (Note 2)
PARAMETER On-Resistance High-Side MOSFET Converter 2 SYMBOL CONDITIONS ISWITCH = 100mA, BST2/VDD2 to VSOURCE2 = 5.2V ISWITCH = 100mA, BST2/VDD2 to VSOURCE2 = 4.5V VOUT1 = 5V, V+ = 12V (Note 4) VOUT2 = 3.3V, V+ = 12V (Note 4) VEN1 = VEN2 = 0V, VDS = 19V, VDRAIN_ = 19V, VSOURCE_ = 0V ILSSW = 30mA 22 MIN TYP 280 m 300 2 1 520 A A MAX UNITS
RON2
Minimum Converter 1 Output Current Minimum Converter 2 Output Current Converter 1/Converter 2 MOSFET DRAIN_ Leakage Current Internal Weak Low-Side Switch On-Resistance
IOUT1 IOUT2
ILK12
20
A
RONLSSW_
INTERNAL SWITCH CURRENT LIMIT Internal Switch Current-Limit Converter 1 Internal Switch Current-Limit Converter 2 SWITCHING FREQUENCY PWM Maximum Duty Cycle Switching Frequency Range Switching Frequency Switching Frequency Accuracy DMAX fSW fSW ROSC = 6.81k, each converter 5.6k < ROSC < 10k, 1% 10k < ROSC < 62.5k, 1% Each converter switching frequency is half of the SYNC input frequency, FSEL_1 = VL (see the Setting the Switching Frequency section) SYNC = SGND, fSW = 1.25MHz 90 200 1.7 1.9 5 7 92 100 2200 2.1 % kHz MHz % ICL1 ICL2 V+ = VIN_HIGH = 5.2V, VL = VDRV = VBST_/VDD_ = 5.2V V+ = VIN_HIGH = 5.2V, VL = VDRV = VBST_/VDD_= 5.2V 2.8 1.75 3.45 2.10 4.3 2.60 A A
SYNC Frequency Range
fSYNC
400
4400
kHz
SYNC High Threshold SYNC Low Threshold SYNC Input Leakage SYNC Input Minimum Pulse Width Sync to Source 1 Phase Delay
VSYNCH VSYNCL ISYNC_LEAK tSYNCIN SYNCPHASE ROSC = 62.5k
2 0.8 2 100 90
V V A ns Degrees
4
_______________________________________________________________________________________
Dual, 2.2MHz, Automotive Synchronous Buck Converter with 80V Load-Dump Protection
ELECTRICAL CHARACTERISTICS (continued)
(VDRV = VL, V+ = VL = IN_HIGH = 5.2V or V+ = IN_HIGH = 5.2V to 19V, EN_ = VL, SYNC = GND, IVL = 0mA, PGND = SGND, CBYPASS = 0.22F (low ESR), CVL = 4.7F (ceramic), CV+ = 1F (low ESR), CIN_HIGH = 1F (ceramic), RIN_HIGH = 3.9k, ROSC = 10k, TJ = -40C to +125C, unless otherwise noted.) (Note 2)
PARAMETER INTERNAL DL_ DRIVERS RDS(ON) DL_ Sink RDS(ON) DL_ Source Break-Before-Make Time FSEL_1 FSEL_1 Input High Threshold FSEL_1 Input Low Threshold FSEL_1 Input Leakage ON/OFF ON/OFF Input High Threshold ON/OFF Input Low Threshold ON/OFF Input Leakage Current EN_ INPUTS EN_ Input High Threshold EN_ Input Hysteresis EN_ Input Leakage Current VIH VEN_HYS IEN_LEAK -1 EN_ rising 1.9 2.0 0.5 +1 2.1 V V A VIH VIL ION/OFF_LEAK VON/OFF = 5V 0.35 2 0.8 2 V V A VIH VIL IFSEL_1_LEAK 2 0.8 2 V V A RONDLN RONDLP ISINK = 200mA ISOURCE = 200mA 1 1.8 50 ns SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX5099
POWER-GOOD OUTPUT (PGOOD1, PGOOD2) PGOOD_ Threshold PGOOD_ Output Voltage PGOOD_ Output Leakage Current FB_ OVP Threshold Rising FB_ OVP Threshold Falling THERMAL PROTECTION Thermal Shutdown Thermal Hysteresis TSHDN THYST Rising +165 20 C C VTPGOOD_ VPGOOD_ ILKPGOOD_ Falling ISINK = 3mA V+ = VL = VIN_HIGH = VEN_ = 5.2V, VPGOOD_ = 23V, VFB_ = 1V 107 114 112.5 90 92.5 95 0.4 2 % VFB_ V A
OUTPUT OVERVOLTAGE PROTECTION VOVP_R VOVP_F 121 % VFB % VFB
Note 2: 100% tested at TA = +25C and TA = +125C. Specifications at TA = -40C are guaranteed by design and not production tested. Note 3: Operating supply range (V+) is guaranteed by VL line regulation test. Connect V+ to IN_HIGH and VL for 5V operation. Note 4: Output current is limited by the power dissipation of the package; see the Power Dissipation section in the Applications Information section.
_______________________________________________________________________________________
5
Dual, 2.2MHz, Automotive Synchronous Buck Converter with 80V Load-Dump Protection MAX5099
Typical Operating Characteristics
(V+ = VIN_HIGH = 14V, unless otherwise noted. V+ = VIN_HIGH means that N1 is shorted externally.)
OUTPUT1 EFFICIENCY vs. LOAD CURRENT
MAX5099 toc01
OUTPUT2 EFFICIENCY vs. LOAD CURRENT
MAX5099 toc02
OUTPUT1 EFFICIENCY vs. LOAD CURRENT
90 OUTPUT1 EFFICIENCY (%) 80 70 60 50 40 30 20 VOUT = 5V fSW = 300kHz L1 = 18H 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 LOAD CURRENT (A) VIN = 8V VIN = 14V VIN = 16V
MAX5099 toc03
100 90 OUTPUT1 EFFICIENCY (%) 80 70 60 50 40 30 20 10 0 VOUT = 5V fSW = 1.85MHz VIN = 8V VIN = 14V VIN = 16V
100 90 OUTPUT2 EFFICIENCY (%) 80 70 60 50 40 30 20 10 0 0.2 0.3 0.4 0.5 0.6 0.7 VIN = 5.5V VIN = 4.5V VOUT = 3.3V fSW = 1.85MHz 0.8 0.9 VIN = 8V VIN = 16V VIN = 14V
100
10 0 1.0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 LOAD CURRENT (A)
LOAD CURRENT (A)
OUTPUT2 EFFICIENCY vs. LOAD CURRENT
MAX5099 toc04
OUTPUT1 VOLTAGE vs. LOAD CURRENT
MAX5099 toc05
OUTPUT2 VOLTAGE vs. LOAD CURRENT
MAX5099 toc06
100 90 OUTPUT2 EFFICIENCY (%) 80 70 60 50 40 30 20 10 0 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 VIN = 4.5V VIN = 8V VIN = 5.5V VOUT = 3.3V fSW = 300kHz L2 = 27H VIN = 14V VIN = 16V
5.00
3.30 3.29 OUTPUT2 VOLTAGE (V) 3.28 3.27 3.26 3.25 3.24 3.23 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 VOUT = 3.3V fSW = 1.85MHz VIN = 5.5V VIN = 8V VIN = 4.5V VIN = 14V VIN = 16V
4.98 OUTPUT1 VOLTAGE (V)
VIN = 8V
VIN = 14V
VIN = 16V
4.96
4.94
4.92 VOUT = 5V fSW = 1.85MHz 4.90 1.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 LOAD CURRENT (A)
1.0
LOAD CURRENT (A)
LOAD CURRENT (A)
VL OUTPUT VOLTAGE vs. CONVERTER SWITCHING FREQUENCY
MAX5099 toc07
EACH CONVERTER SWITCHING FREQUENCY vs. ROSC
FSEL_1 = VL, FSEL_1 = GND,
MAX5099 toc08
EACH CONVERTER SWITCHING FREQUENCY vs. TEMPERATURE
FSEL_1 = VL SWITCHING FREQUENCY (MHz) 1.85MHz 2.2MHz
MAX5099 toc09
5.4 5.2 VL OUTPUT VOLTAGE (V) 5.0 4.8 4.6 4.4 4.2
BOTH CONVERTERS SWITCHING FSEL_1 = VL VIN = 5.5V VIN = 8V VIN = 19V
10 SWITCHING FREQUENCY (MHz)
10
CONVERTER 1, CONVERTER 2 1
1 1.25MHz 0.6MHz
VIN = 5V
VIN = 4.5V 4.0 400 700 1000 1300 1600 1900 2200 CONVERTER SWITCHING FREQUENCY (kHz) 0.1 0
CONVERTER 1 0.1 20 40 ROSC (k) 60 80 -40
0.3MHz -5 30 65 100 135
TEMPERATURE (C)
6
_______________________________________________________________________________________
Dual, 2.2MHz, Automotive Synchronous Buck Converter with 80V Load-Dump Protection
Typical Operating Characteristics (continued)
(V+ = VIN_HIGH = 14V, unless otherwise noted. V+ = VIN_HIGH means that N1 is shorted externally.)
MAX5099
LINE-TRANSIENT RESPONSE (BUCK CONVERTER)
MAX5099 toc10
CONVERTER 1 LOAD-TRANSIENT RESPONSE
MAX5099 toc11
0V VIN 5V/div 0V VOUT1 = 5.0V/1.5A AC-COUPLED 200mV/div VOUT2 = 3.3V/0.75A AC-COUPLED 200mV/div 1ms/div 100s/div
VOUT1 = 5.0V AC-COUPLED 200mV/div
IOUT1 1A/div 0A
CONVERTER 2 LOAD-TRANSIENT RESPONSE
MAX5099 toc12
SOFT-START/SOFT-STOP FROM EN1
MAX5099 toc13
fSW = 1.85MHz EN1 5V/div 0V VOUT2 = 3.3V AC-COUPLED 200mV/div VOUT1 = 5V/2A 5V/div 0V PGOOD1 5V/div 0V
IOUT2 500mA/div 0A
100s/div
1ms/div
SOFT-START FROM ON/OFF
MAX5099 toc14
OUT-OF-PHASE OPERATION (FSEL_1 = VL)
MAX5099 toc15
ON/OFF 5V/div 0V VL = EN1 = EN2 5V/div GATE 10V/div V+ 10V/div VOUT1 = 5V/2A 5V/div
0V
SOURCE1 10V/div SOURCE2 10V/div
0V
0V
0V 0V
0V 0V
DL1 10V/div DL2 10V/div
2ms/div
200ns/div
_______________________________________________________________________________________
7
Dual, 2.2MHz, Automotive Synchronous Buck Converter with 80V Load-Dump Protection MAX5099
Typical Operating Characteristics (continued)
(V+ = VIN_HIGH = 14V, unless otherwise noted. V+ = VIN_HIGH means that N1 is shorted externally.)
OUT-OF-PHASE OPERATION (FSEL_1 = SGND)
MAX5099 toc16
EXTERNAL SYNCHRONIZATION (FSEL_1 = VL)
MAX5099 toc17
SOURCE1 10V/div 0V SOURCE2 10V/div
SYNC 5V/div 0V SOURCE1 10V/div 0V SOURCE2 10V/div 0V
0V
0V 0V
DL1 10V/div DL2 10V/div
200ns/div
200ns/div
EXTERNAL SYNCHRONIZATION (FSEL_1 = SGND )
MAX5099 toc18
OVP BEHAVIOR
MAX5099 toc19
SYNC 5V/div 0V SOURCE1 10V/div 0V SOURCE2 10V/div 0V
V+ 10V/div GATE 10V/div
0V EXTERNAL OVERVOLTAGE REMOVED 0V 0V 0V 0V
VOUT2 10V/div VOUT1 10V/div PGOOD2 10V/div 1ms/div
200ns/div
FB_ VOLTAGE vs. TEMPERATURE
MAX5099 toc20
BYPASS VOLTAGE vs. TEMPERATURE
2.008 2.006 BYPASS VOLTAGE (V) 2.004 2.002 2.000 1.998 1.996 1.994 1.992 1.990 VL = V+ = VIN_HIGH = 5.5V
MAX5099 toc21
0.825 VL = V+ = VIN_HIGH = 5.5V 0.820 0.815 FB_ VOLTAGE (V) 0.810 0.805 0.800 0.795 0.790 0.785 -40 -5 30 65 100
2.010
135
-40
-5
30
65
100
135
TEMPERATURE (C)
TEMPERATURE (C)
8
_______________________________________________________________________________________
Dual, 2.2MHz, Automotive Synchronous Buck Converter with 80V Load-Dump Protection
Typical Operating Characteristics (continued)
(V+ = VIN_HIGH = 14V, unless otherwise noted. V+ = VIN_HIGH means that N1 is shorted externally.)
BYPASS VOLTAGE vs. BYPASS CURRENT
TA = +85C 1.998 BYPASS VOLTAGE (V) TA = +125C
MAX5099 toc22
MAX5099
SOURCE1, ISOURCE1, DL1, IIDL1
MAX5099 toc23
2.000 TA = +135C
1.996 TA = -40C TA = +25C
SOURCE1 10V/div 0V DL1 10V/div OV ISOURCE1 1A/div 0A 0 10 20 30 40 50 60 70 80 90 100 BYPASS CURRENT (A) 200ns/div
1.994
1.992
1.990
V+ SWITCHING SUPPLY CURRENT vs. SWITCHING FREQUENCY
MAX5099 toc24
V+ STANDBY SUPPLY CURRENT vs. TEMPERATURE
V+ STANDBY SUPPLY CURRENT (mA) V+ = IN_HIGH = ON/OFF EN1 = EN2 = SGND 3 fSW = 1.85MHz 2
MAX5099 toc25
100 V+ SWITCHING SUPPLY CURRENT (mA) V+ = IN_HIGH = ON/OFF 80 TA = +135C
4
60
TA = +25C
40
20 TA = -40C 0 300 680 1060 1440 1820 2200 SWITCHING FREQUENCY (kHz)
1 fSW = 300kHz 0 -50 0 50 TEMPERATURE (C) 100 150
IN_HIGH SHUTDOWN CURRENT vs. TEMPERATURE
MAX5099 toc26
IN_HIGH STANDBY CURRENT vs. TEMPERATURE
145 IN_HIGH STANDBY CURRENT (A) 135 125 115 105 95 85 IN_HIGH = 14V IN_HIGH = 8V IN_HIGH = 16V ON/OFF = IN_HIGH EN1 = EN2 = SGND
MAX5099 toc27
20 ON/OFF = SGND IN_HIGH SHUTDOWN CURRENT (A) IN_HIGH = 16V 16 IN_HIGH = 14V 12 IN_HIGH = 8V 8
4
0 -50 0 50 TEMPERATURE (C) 100 150
75 -50 0 50 TEMPERATURE (C) 100 150
_______________________________________________________________________________________
9
Dual, 2.2MHz, Automotive Synchronous Buck Converter with 80V Load-Dump Protection MAX5099
Typical Operating Characteristics (continued)
(V+ = VIN_HIGH = 14V, unless otherwise noted. V+ = VIN_HIGH means that N1 is shorted externally.)
IN_HIGH CLAMP VOLTAGE vs. CLAMP CURRENT
MAX5099 toc28
V+ TO IN_HIGH CLAMP VOLTAGE vs. GATE SINK CURRENT
TA = +135C TA = +125C 4 V+ TO IN_HIGH CLAMP VOLTAGE (V)
MAX5099 toc29
20.3 TA = +135C IN_HIGH CLAMP VOLTAGE (V) 20.2 TA = +125C TA = +85C 20.1 TA = +25C TA = -40C 20.0
5
3 TA = +85C 2 TA = -40C TA = +25C
1
19.9 0 10 20 30 40 50 CLAMP CURRENT (mA)
0 0 2 4 6 8 10 GATE SINK CURRENT (mA)
(VGATE - V) vs. VIN_HIGH
MAX5099 toc30
SYSTEM TURN-ON FROM BATTERY
MAX5099 toc31
10
8 (VGATE - V) (V)
TA = +135C TA = +125C
0V 0V
6 TA = +85C 4 TA = +25C TA = -40C ON/OFF = IN_HIGH 0 5.0 8.5 12.0 VIN_HIGH (V) 15.5 19.0
VIN 10V/div IN_HIGH 10V/div GATE 10V/div V+ 10V/div VL 10V/div 10ms/div
0V 0V 0V
2
SYSTEM TURN-OFF FROM BATTERY
MAX5099 toc32
SYSTEM LOAD DUMP
MAX5099 toc33
VIN 50V/div 0V 0V VIN 10V/div IN_HIGH 10V/div GATE 10V/div V+ 10V/div VL 10V/div 0V IN_HIGH 10V/div GATE 10V/div V+ 10V/div 0V 0V 0V 100ms/div VOUT1 AC-COUPLED 100mV/div
0V
0V 0V 0V 10ms/div
10
______________________________________________________________________________________
Dual, 2.2MHz, Automotive Synchronous Buck Converter with 80V Load-Dump Protection MAX5099
Pin Description
PIN 1, 32 NAME SOURCE2 FUNCTION Converter 2 Internal MOSFET Source Connection. For buck converter operation, connect SOURCE2 to the switched side of the inductor. For boost operation, connect SOURCE2 to PGND (Figure 5). Converter 2 Internal MOSFET Drain Connection. For buck converter operation, use the MOSFET as a highside switch and connect DRAIN2 to the DC-DC converters supply input rail. For boost converter operation, use the MOSFET as a low-side switch and connect DRAIN2 to the inductor and diode junction (Figure 5). Converter Open-Drain Power-Good Output. PGOOD2 goes low when converter 2's output falls below 92.5% of its set regulation voltage. Use PGOOD2 and EN1 to sequence the converters. Converter 2 Active-High Enable Input. Connect to VL for always-on operation. Converter 2 Feedback Input. Connect FB2 to a resistive divider between converter 2's output and SGND to adjust the output voltage. To set the output voltage below 0.8V, connect FB2 to a resistive voltage-divider from BYPASS to regulator 2's output (Figure 2). See the Setting the Output Voltage section. Converter 2 Internal Transconductance Amplifier Output. See the Compensation section. Oscillator Frequency Set Input. Connect a resistor from OSC to SGND (ROSC) to set the switching frequency (see the Setting the Switching Frequency section). Set ROSC for an oscillator frequency equal to the SYNC input frequency when using external synchronization. ROSC is still required when an external clock is connected to the SYNC input. See the Synchronization (SYNC) section. External Clock Synchronization Input. Connect SYNC to a 400kHz to 4400kHz clock to synchronize the switching frequency with the system clock. Each converter frequency is 1/2 of the frequency applied to SYNC (FSEL_1 = VL). For FSEL_1 = SGND, the switching frequency of converter 1 becomes 1/4 of the SYNC frequency. Connect SYNC to SGND when not used. Gate Drive Output. Connect to the gate of the external n-channel load-dump protection MOSFET. GATE = IN_HIGH + 9V (typ) with IN_HIGH = 12V. GATE pulls to IN_HIGH by an internal n-channel MOSFET when V+ raises 2V above IN_HIGH. Leave GATE unconnected if the load-dump protection is not used (MOSFET not installed). n-Channel Switch Enable Input. Drive ON/OFF high for normal operation. Drive ON/OFF low to turn off the external n-channel load-dump protection MOSFET and reduce the supply current to 7A (typ). When ON/OFF is driven low, both DC-DC converters are disabled and the PGOOD_ outputs are driven low. Connect to V+ if the external load-dump protection is not used (MOSFET not installed). Startup Input. IN_HIGH is protected by internally clamping to 21V (max). Connect a resistor (4k max) from IN_HIGH to the drain of the protection switch. Bypass IN_HIGH with a 4.7F electrolytic or 1F minimum ceramic capacitor. Connect to V+ if the external load-dump protection is not used (MOSFET not installed). Input Supply Voltage. V+ can range from 5.2V to 19V. Connect V+, IN_HIGH, and VL together for 4.5V to 5.5V input operation. Bypass V+ to SGND with a 1F minimum ceramic capacitor. Internal Regulator Output. The VL regulator is used to supply the drive current at input VDRV. When driving VDRV, use an RC lowpass filter to decouple switching noise from VDRV to the VL regulator (see the Typical Application Circuit). Bypass VL to SGND with a 4.7F minimum ceramic capacitor.
2, 3
DRAIN2
4 5 6 7
PGOOD2 EN2 FB2 COMP2
8
OSC
9
SYNC
10
GATE
11
ON/OFF
12
IN_HIGH
13
V+
14
VL
______________________________________________________________________________________
11
Dual, 2.2MHz, Automotive Synchronous Buck Converter with 80V Load-Dump Protection MAX5099
Pin Description (continued)
PIN 15 16 17 18 19 20 21 NAME SGND BYPASS FSEL_1 COMP1 FB1 EN1 PGOOD1 FUNCTION Signal Ground. Connect SGND to exposed pad and to the board signal ground plane. Connect the board signal ground and power ground planes together at a single point. Reference Output Bypass Connection. Bypass to SGND with a 0.22F or greater ceramic capacitor. Converter 1 Frequency Select Input. Connect FSEL_1 to VL for normal operation. Connect FSEL_1 to SGND to reduce converter 1's switching frequency to 1/2 of converter 2's switching frequency (converter 1 switching frequency is 1/4 the SYNC frequency). Do not leave FSEL_1 unconnected. Converter 1 Internal Transconductance Amplifier Output. See the Compensation section. Converter 1 Feedback Input. Connect FB1 to a resistive divider between converter 1's output and SGND to adjust the output voltage. To set the output voltage below 0.8V, connect FB1 to a resistive voltage-divider from BYPASS to regulator 1's output (Figure 2). See the Setting the Output Voltage section. Converter 1 Active-High Enable Input. Connect to VL for an always-on operation. Converter 1 Power-Good Output. Open-drain output goes low when converter 1's output falls below 92.5% of its set regulation voltage. Use PGOOD1 and EN2 to sequence the converters (converter 1 starts first). Converter 1 Internal MOSFET Drain Connection. For buck converter operation, use the MOSFET as a highside switch and connect DRAIN1 to the DC-DC converters supply input rail. For boost converter operation, use the MOSFET as a low-side switch and connect DRAIN1 to the inductor and diode junction (Figure 5). Converter 1 Internal MOSFET Source Connection. For buck operation, connect SOURCE1 to the switched side of the inductor. For boost operation, connect SOURCE1 to PGND (Figure 5).
22, 23
DRAIN1
24, 25
SOURCE1
26
Converter 1 Bootstrap Flying-Capacitor Connection. For buck converter operation, connect BST1/VDD1 to a 0.1F ceramic capacitor and diode according to the Typical Application Circuit. For boost converter BST1/VDD1 operation, driver bypass capacitor connection. Connect to VDRV and bypass with a 0.1F ceramic capacitor to PGND (Figure 5). Low-Side Driver Supply Input. Connect VDRV to VL through an RC filter to bypass switching noise to the internal VL regulator. For buck converter operation, connect anode terminals of external bootstrap diodes to VDRV. For boost converter operation, connect VDRV to BST1/VDD1 and BST2/VDD2. Bypass with a minimum 2.2F ceramic capacitor to PGND (see the Typical Application Circuit). Do not connect to an external supply. Converter 1 Low-Side Synchronous-Rectifier Gate Driver Output Power Ground. Connect to the board power ground plane. Converter 2 Low-Side Synchronous-Rectifier Gate Driver Output
27
VDRV
28 29 30
DL1 PGND DL2
31
Converter 2 Bootstrap Flying-Capacitor Connection. For buck converter operation, connect BST2/VDD2 to a 0.1F ceramic capacitor and diode according to the Typical Application Circuit. For boost converter BST2/VDD2 operation, driver bypass capacitor connection. Connect to VDRV and bypass with a 0.1F ceramic capacitor from BST2/VDD2 to PGND (Figure 5). EP Exposed Pad. Connect EP to SGND. For enhanced thermal dissipation, connect EP to a copper area as large as possible. Do not use EP as the sole ground connection.
--
12
______________________________________________________________________________________
Dual, 2.2MHz, Automotive Synchronous Buck Converter with 80V Load-Dump Protection MAX5099
Functional Diagram
V+
MAX5099
1.8V IN_HIGH CHARGE PUMP ON/OFF 20V SHUNT REGULATOR OVERVOLTAGE STARTUP CIRCUIT/ PROTECTION CIRCUIT/ CHARGE PUMP LDO VL GATE
CONVERTER 1 MAX DUTY-CYCLE CONTROL CLK1 OSCILLATOR FREQUENCY CONTROL R S FSEL_1 FREQUENCY DIVIDER PWM COMPARATOR Q FSW/4 Q CURRENT LIMIT
VL BST1/VDD1 DRAIN1
BYPASS
SOURCE1 VDRV DL1 PGOOD1
TRANSCONDUCTANCE ERROR AMPLIFIER 0.8V EN1 DIGITAL SOFT-START
PGND
FB1 COMP1
0.2V
0.74V SGND
SYNC OSC
MAIN OSCILLATOR
OVERVOLTAGE 0.9V VDRV VL PGOOD2 DRAIN2 BST2/VDD2 SOURCE2 FB2 COMP2 PGND
CLK2 CONVERTER 2 EN2
______________________________________________________________________________________
13
Dual, 2.2MHz, Automotive Synchronous Buck Converter with 80V Load-Dump Protection MAX5099
Detailed Description
PWM Controller
The MAX5099 dual DC-DC converters use a pulse-widthmodulation (PWM) voltage-mode control scheme. On each converter the device includes one integrated nchannel MOSFET switch and requires an external low-forward-drop Schottky diode for output rectification. The controller generates the clock signal by dividing down the internal oscillator (fOSC) or the SYNC input when driven by an external clock; therefore, each controller's switching frequency equals half the oscillator frequency (fSW = fOSC/2) or half of the SYNC input frequency (fSW = fSYNC/2). An internal transconductance error amplifier produces an integrated error voltage at COMP_, providing high DC accuracy. The voltage at COMP_ sets the duty cycle using a PWM comparator and a ramp generator. At each rising edge of the clock, converter 1's MOSFET switch turns on and remains on until either the appropriate or maximum duty cycle is reached, or the maximum current limit for the switch is reached. Converter 2 operates 180 out-of-phase, so its MOSFET switch turns on at each falling edge of the clock. In the case of buck operation (see the Typical Application Circuit), the internal MOSFET is used in high-side configuration. During each MOSFET's on-time, the associated inductor current ramps up. During the second half of the switching cycle, the high-side MOSFET turns off and forward biases the Schottky rectifier. During this time, the SOURCE_ voltage is clamped to a diode drop (VD) below ground. A low-forward-voltage-drop (0.4V) Schottky diode must be used to ensure the SOURCE_ voltage does not go below -0.6V absolute max. The inductor releases the stored energy as its current ramps down, and provides current to the output. The bootstrap capacitor is also recharged when the SOURCE_ voltage goes low during the high-side MOSFET off-time. The maximum duty-cycle limits ensure proper bootstrap charging at startup or low input voltages. The circuit goes in discontinuous conduction mode operation at light load, when the inductor current completely discharges before the next cycle commences. Under overload conditions, when the inductor current exceeds the peak current limit of the respective switch, the high-side MOSFET turns off quickly and waits until the next clock cycle. synchronous MOSFET. The SOURCE_ voltage is clamped to 0.5V below ground until the adaptive breakbefore-make time (tBBM) of 25ns is over. After tBBM, the synchronous-rectifier MOSFET turns on, thus bypassing the Schottky rectifier and reducing the conduction loss during the inductor freewheeling time. The synchronousrectifier MOSFET keeps the circuit in continuous conduction mode operation even at light load because the inductor current is allowed to go negative. The MAX5099, with the synchronous-rectifier driver output (DL_), has an adaptive break-before-make circuit to avoid cross-conduction between the internal power MOSFET and the external synchronous-rectifier MOSFET. When the synchronous-rectifier MOSFET is turning off, the internal high-side power MOSFET is kept off until VDL falls below 0.97V. Similarly, DL_ does not go high until the internal power MOSFET gate voltage falls below 1.24V.
Load-Dump Protection
Most automotive applications are powered by a multicell, 12V lead-acid battery with a voltage from 9V to 16V (depending on load current, charging status, temperature, battery age, etc.). The battery voltage is distributed throughout the automobile and is locally regulated down to voltages required by the different system modules. Load dump occurs when the alternator is charging the battery and the battery becomes disconnected. Power in the alternator inductance flows into the distributed power system and elevates the voltage seen at each module. The voltage spikes have rise times typically greater than 5ms and decays within several hundred milliseconds but can extend out to 1s or more depending on the characteristics of the charging system. These transients are capable of destroying sensitive electronic equipment on the first fault event. During load dump, the MAX5099 provides the ability to clamp the input-voltage rail of the internal DC-DC converters to a safe level, while preventing power discontinuity at the DC-DC converters' outputs. The load-dump protection circuit utilizes an internal charge pump to drive the gate of an external n-channel MOSFET. This series-protection MOSFET absorbs the load-dump overvoltage transient and operates in saturation over the normal battery range to minimize power dissipation. During load dump, the gate voltage of the protection MOSFET is regulated to prevent the source terminal from exceeding 19V. The DC-DC converters are powered from the source terminal of the load-dump protection MOSFET, so that their input voltage is limited during load dump and can operate normally.
Synchronous-Rectifier Output The MAX5099 is intended mostly for synchronous buck operation with an external synchronous-rectifier MOSFET. During the internal high-side MOSFET on-time, the inductor current ramps up. When the high-side MOSFET turns off, the inductor reverses polarity and forward biases the Schottky rectifier in parallel with the low-side external
14
______________________________________________________________________________________
Dual, 2.2MHz, Automotive Synchronous Buck Converter with 80V Load-Dump Protection
ON/OFF
The MAX5099 provide an input (ON/OFF) to turn on and off the external load-dump protection MOSFET. Drive ON/OFF high for normal operation. Drive ON/OFF low to turn off the external n-channel load-dump protection MOSFET and reduce the supply current to 7A (typ). When ON/OFF is driven low, both converters are also turned off, and the PGOOD_ outputs are driven, low. V+ will be self-discharged through the converters' output currents and the IC supply current. 5.2V or below, the internal linear regulator operates in dropout mode, where VL follows V+. Depending on the load on VL, the dropout voltage can be high enough to reduce V L below the undervoltage-lockout (UVLO) threshold. Do not use VL to power external circuitry. For input voltages less than 5.5V, connect V+ and VL together. The load on VL is proportional to the switching frequency of converter 1 and converter 2. See the VL Output Voltage vs. Converter Switching Frequency graph in the Typical Operating Characteristics. For input voltage ranges higher than 5.5V, disconnect VL from V+. Bypass V+ to SGND with a 1F or greater ceramic capacitor placed close to the MAX5099. Bypass VL with a low-ESR 4.7F ceramic capacitor to SGND.
MAX5099
Internal Oscillator/ Out-of-Phase Operation
The internal oscillator generates the 180 out-of-phase clock signal required by each regulator. The switching frequency of each converter (fSW) is programmable from 200kHz to 2.2MHz using a single 1% resistor at ROSC. See the Setting the Switching Frequency section. With dual-synchronized out-of-phase operation, the MAX5099's internal MOSFETs turn on 180 out-ofphase. The instantaneous input current peaks of both regulators do not overlap, resulting in reduced RMS ripple current and input-voltage ripple. This reduces the required input capacitor ripple current rating, allows for fewer or less expensive capacitors, and reduces shielding requirements for EMI.
Undervoltage Lockout/ Soft-Start/Soft-Stop
The MAX5099 includes an undervoltage lockout with hysteresis and a power-on-reset circuit for converter turn-on and monotonic rise of the output voltage. The falling UVLO threshold is internally set to 4.1V (typ) with 180mV hysteresis. Hysteresis at UVLO eliminates "chattering" during startup. When VL drops below UVLO, the internal MOSFET switches are turned off. The MAX5099 digital soft-start reduces input inrush currents and glitches at the input during turn-on. When UVLO is cleared and EN_ is high, digital soft-start slowly ramps up the internal reference voltage in 64 steps. The total soft-start period is 4096 internal oscillator switching cycles. Driving EN_ low initiates digital soft-stop that slowly ramps down the internal reference voltage in 64 steps. The total soft-stop period is equal to the soft-start period. To calculate the soft-start/soft-stop period, use the following equation: t SS (ms) = 4096 fOSC (kHz)
Synchronization (SYNC)
The main oscillator can be synchronized to the system clock by applying an external clock (fSYNC) at SYNC. The fSYNC frequency must be twice the required operating frequency of an individual converter. Use a TTL logic signal for the external clock with at least a 100ns pulse width. ROSC is still required when using external synchronization. Program the internal oscillator frequency to have fSW = 1/2 fSYNC. The device is properly synchronized if the SYNC frequency fSYNC varies within the range 20%. Short SYNC to SGND if unused.
Input Voltage (V+)/ Internal Linear Regulator (VL)
All internal control circuitry operates from an internally regulated nominal voltage of 5.2V (VL). At higher input voltages (V+) of 5.2V to 19V, VL is regulated to 5.2V. At
where fOSC is the internal oscillator and fOSC is twice each converter's switching frequency (FSEL_1 = VL).
______________________________________________________________________________________
15
Dual, 2.2MHz, Automotive Synchronous Buck Converter with 80V Load-Dump Protection MAX5099
VIN VL VL VIN
OUTPUT2
VL DRAIN2 SOURCE2 N DL2
V+ DRAIN1 SOURCE1 DL1 N
OUTPUT1
OUTPUT2
VL DRAIN2 SOURCE2 N DL2
V+ DRAIN1 SOURCE1 DL1 N
OUTPUT1
MAX5099
MAX5099
FB2
FB1 R2
FB2 VL VL C2 EN2
FB1 R1 EN1 C1 VL
VL
EN2
EN1 PGOOD1
SEQUENCING--OUTPUT 2 DELAYED WITH RESPECT TO OUTPUT 1.
R1/C1 AND R2/C2 ARE SIZED FOR REQUIRED SEQUENCING.
Figure 1. Power-Supply Sequencing Configurations
Enable (EN1, EN2)
The MAX5099 dual converter provides separate enable inputs, EN1 and EN2, to individually control or sequence the output voltages. These active-high enable inputs are TTL compatible. Driving EN_ high initiates soft-start of the converter, and PGOOD_ goes logic-high when the converter output voltage reaches the VTPGOOD_ threshold. Driving EN_ low initiates a soft-stop of the converter. Use EN1, EN2, and PGOOD1 for sequencing (see Figure 1). Connect PGOOD1 to EN2 to make sure converter 1's output is within regulation before converter 2 starts. Add an RC network from VL to EN1 and EN2 to delay the individual converter. Sequencing reduces input inrush current and possible chattering. Connect EN_ to VL for always-on operation.
of 3.45A (typ) and 2.1A (typ) for converter 1 and converter 2, respectively, the on-cycle is terminated immediately and the inductor is allowed to discharge. The MOSFET switch is turned on at the next clock pulse initiating a new clock cycle. In deep overload or short-circuit conditions when VFB drops below 0.2V, the switching frequency is reduced to 1/4 x fSW to provide sufficient time for the inductor to discharge. During overload conditions, if the voltage across the inductor is not high enough to allow for the inductor current to properly discharge, current runaway may occur. Current runaway can destroy the device in spite of internal thermal-overload protection. Reducing the switching frequency during overload conditions prevents current runaway.
PGOOD_
Converter 1 and converter 2 include power-good flags, PGOOD1 and PGOOD2, respectively. Since PGOOD_ is an open-drain output and can sink 3mA while providing the TTL logic-low signal, pull PGOOD_ to a logic voltage to provide a logic-level output. PGOOD1 goes low when converter 1's feedback (FB_) drops to 92.5% (VTPGOOD_) of its nominal set point. The same is true for converter 2. Connect PGOOD_ to SGND or leave unconnected, if not used.
Output Overvoltage Protection
The MAX5099 outputs are protected from output voltage overshoots due to input transients and shorting the output to a high voltage. When the output voltage rises over the overvoltage threshold, 114% (typ) nominal FB, the overvoltage condition is triggered. When the overvoltage condition is triggered on either channel, both converters are immediately turned off, 20 pulldown switches from SOURCE_ to PGND are turned on to help the output-voltage discharge, and the gate of the loaddump protection external MOSFET is pulled low. The device restarts as soon as both converter outputs discharge, bringing both FB_ input voltages below 12.5% of their nominal set points.
Current Limit
The internal high-side MOSFET switch current of each converter is monitored during its on-time. When the peak switch current crosses the current-limit threshold
16
______________________________________________________________________________________
Dual, 2.2MHz, Automotive Synchronous Buck Converter with 80V Load-Dump Protection
Thermal-Overload Protection
During continuous short circuit or overload at the output, the power dissipation in the IC can exceed its limit. The MAX5099 provides thermal shutdown protection with temperature hysteresis. Internal thermal shutdown is provided to avoid irreversible damage to the device. When the die temperature exceeds +165C (typ), an onchip thermal sensor shuts down the device, forcing the internal switches to turn off, allowing the IC to cool. The thermal sensor turns the part on again with soft-start after the junction temperature cools by +20C. During thermal shutdown, both regulators shut down, PGOOD_ goes low, and soft-start resets. The internal 20V zener clamp from IN_HIGH to SGND is not turned off during thermal shutdown because this clamping action must always be active. input voltage is limited by the minimum on-time (tON(MIN)): VIN(MAX) VOUT t ON(MIN) x fSW
MAX5099
where tON(MIN) is 100ns. The minimum input voltage is limited by the maximum duty cycle (DMAX = 0.92): V +V VIN(MIN) = OUT DROP1 + VDROP2 - VDROP1 DMAX where VDROP1 is the total parasitic voltage drops in the inductor discharge path, which includes the forward voltage drop (VDS) of the low-side n-channel MOSFET, the series resistance of the inductor, and the PCB resistance. VDROP2 is the total resistance in the charging path that includes the on-resistance of the high-side switch, the series resistance of the inductor, and the PCB resistance.
Applications Information
Setting the Switching Frequency
The controller generates the clock signal by dividing down the internal oscillator fOSC or the SYNC input signal when driven by an external oscillator. The switching frequency equals half the internal oscillator frequency (fSW = fOSC/2). The internal oscillator frequency is set by a resistor (ROSC) connected from OSC to SGND. To find ROSC for each converter switching frequency fSW, use the formulas: ROSC (k) = ROSC (k) = 10.721 fSW (MHz) fSW (MHz) 12.184 f 1.25MHz 0.920 SW f < 1.25MHz 0.973 SW
Setting the Output Voltage For 0.8V or greater output voltages, connect a voltagedivider from OUT_ to FB_ to SGND (Figure 2). Select RB (FB_ to SGND resistor) to between 1k and 20k. Calculate RA (OUT_ to FB_ resistor) with the following equation:
VOUT _ RA = RB - 1 VFB _ where VFB_ = 0.8V (see the Electrical Characteristics table). For output voltages below 0.8V, set the MAX5099 output voltage by connecting a voltage-divider from OUT_ to FB_ to BYPASS (Figure 2). Select RC (FB_ to BYPASS resistor) higher than a 50k range. Calculate RA with the following equation: V -V RA = RC FB _ OUT _ VBYPASS - VFB _ where VFB_ = 0.8V, VBYPASS = 2V (see the Electrical Characteristics table), and VOUT_ can range from 0V to VFB_.
(
)
(
)
A rising clock edge on SYNC is interpreted as a synchronization input. If the SYNC signal is lost, the internal oscillator takes control of the switching rate, returning the switching frequency to that set by ROSC. When an external synchronization signal is used, ROSC must be selected such that fSW = 1/2 fSYNC.
Buck Converter
Effective Input Voltage Range Although the MAX5099 converter operates from input supplies ranging from 5.2V to 19V, the input voltage range can be effectively limited by the MAX5099 dutycycle limitations for a given output voltage. The maximum
______________________________________________________________________________________
17
Dual, 2.2MHz, Automotive Synchronous Buck Converter with 80V Load-Dump Protection
VOUT_ SOURCE_ BYPASS VOUT_
RA
RC
FB_
FB_
MAX5099
RB
MAX5099
RA
SOURCE_ VOUT_ 0.8V VOUT_ < 0.8V
capacitance requirement. Note that the two converters of the MAX5099 run 180 out-of-phase, thereby effectively doubling the switching frequency at the input. The input ripple waveform would be unsymmetrical due to the difference in load current and duty cycle between converter 1 and converter 2. The worst-case mismatch is when one converter is at full load while the other is at no load or in shutdown. The input ripple is comprised of VQ (caused by the capacitor discharge) and VESR (caused by the ESR of the capacitor). Use ceramic capacitors with high ripple-current capability at the input connected between DRAIN_ and PGND. Assume the contribution from the ESR and capacitor discharge equal to 50%. Calculate the input capacitance and ESR required for a specified ripple using the following equations: ESRIN = VESR I IOUT + L 2
MAX5099
Figure 2. Adjustable Output Voltage
Inductor Selection Three key inductor parameters must be specified for operation with the MAX5099: inductance value (L), peak inductor current (IL), and inductor saturation current (ISAT). The minimum required inductance is a function of operating frequency, input-to-output voltage differential, and the peak-to-peak inductor current (IL). A good compromise is to choose IL equal to 30% of the full load current. To calculate the inductance, use the following equation:
L= VOUT (VIN - VOUT ) VIN x fSW x IL
where IL = and CIN = where V D = OUT VIN where IOUT is the maximum output current from either converter 1 or converter 2, and D is the duty cycle for that converter. fSW is the frequency of each individual converter. For example, at VIN = 12V, VOUT = 3.3V at I OUT = 2A, and with L = 3.3H, the ESR and input capacitance are calculated for a peak-to-peak input ripple of 100mV or less, yielding an ESR and capacitance value of 20m and 6.8F for 1.25MHz frequency. At low input voltages, also add one electrolytic bulk capacitor of at least 100F on the converters' input voltage rail. This capacitor acts as an energy reservoir to avoid possible undershoot below the undervoltage-lockout threshold during power-on and transient loading. IOUT x D(1 - D) VQ x fSW
(VIN - VOUT ) x VOUT
VIN x fSW x L
where VIN and VOUT are typical values (so that efficiency is optimum for typical conditions). The switching frequency is set by ROSC (see the Setting the Switching Frequency section). The peak-to-peak inductor current, which reflects the peak-to-peak output ripple, is worse at the maximum input voltage. See the Output Capacitor section to verify that the worst-case output ripple is acceptable. The inductor saturation current is also important to avoid runaway current during output overload and continuous short circuit. Select the ISAT to be higher than the maximum peak current limits of 4.3A and 2.6A for converter 1 and converter 2.
Input Capacitor The discontinuous input current waveform of the buck converter causes large ripple currents at the input. The switching frequency, peak inductor current, and allowable peak-to-peak voltage ripple dictate the input
18
______________________________________________________________________________________
Dual, 2.2MHz, Automotive Synchronous Buck Converter with 80V Load-Dump Protection
Output Capacitor The allowable output ripple voltage and the maximum deviation of the output voltage during step load currents determine the output capacitance and its ESR. The output ripple is comprised of VQ (caused by the capacitor discharge) and VESR (caused by the ESR of the capacitor). Use low-ESR ceramic or aluminum electrolytic capacitors at the output. For aluminum electrolytic capacitors, the entire output ripple is contributed by VESR. Use the ESROUT equation to calculate the ESR requirements and choose the capacitor accordingly. If using ceramic capacitors, assume the contribution to the output ripple voltage from the ESR and the capacitor discharge are equal. Calculate the output capacitance and ESR required for a specified ripple using the following equations:
VESR IL IL COUT = 8 x VQ x fSW ESROUT = where VO _ RIPPLE VESR + VQ IL is the peak-to-peak inductor current as calculated above and fSW is the individual converter's switching frequency. The allowable deviation of the output voltage during fast transient loads also determines the output capacitance and its ESR. The output capacitor supplies the step load current until the controller responds with a greater duty cycle. The response time (t RESPONSE) depends on the closed-loop bandwidth of the converter. The high switching frequency of the MAX5099 allows for higher closed-loop bandwidth, reducing tRESPONSE and the output capacitance requirement. The resistive drop across the output capacitor ESR and the capacitor discharge causes a voltage droop during a step load. Use a combination of low-ESR tantalum or polymer and ceramic capacitors for better transient load and ripple/noise performance. Keep the maximum output-voltage deviation within the tolerable limits of the electronics being powered. When using a ceramic capacitor, assume 80% and 20% contribution from the output capacitance discharge and the ESR drop, respectively. Use the following equations to calculate the required ESR and capacitance value: where D= VO + VD - VIN VO + VD - VDS
MAX5099
ESROUT =
VESR ISTEP xt I COUT = STEP RESPONSE VQ
where I STEP is the load step and t RESPONSE is the response time of the controller. Controller response time depends on the control-loop bandwidth.
Boost Converter
The MAX5099 can be configured for step-up conversion since the internal MOSFET can be used as a lowside switch. Use the following equations to calculate the values for the inductor (LMIN), input capacitor (CIN), and output capacitor (COUT) when using the converter in boost operation.
Inductor Choose the minimum inductor value so the converter remains in continuous mode operation at minimum output current (IOMIN).
LMIN = VIN2 x D 2 x fSW x VO x IOMIN
VD is the forward voltage drop of the external Schottky diode, D is the duty cycle, and VDS is the voltage drop across the internal MOSFET switch. Select the inductor with low DC resistance and with a saturation current (ISAT) rating higher than the peak switch current limit of 4.3A (ICL1) and 2.6A (ICL2) of converter 1 and converter 2, respectively.
Input Capacitor The input current for the boost converter is continuous, and the RMS ripple current at the input is low. Calculate the capacitor value and ESR of the input capacitor using the following equations:
CIN = IL 8 x fSW x VQ VESR IL
ESR =
______________________________________________________________________________________
19
Dual, 2.2MHz, Automotive Synchronous Buck Converter with 80V Load-Dump Protection MAX5099
where IL = where
(VIN - VDS ) x D
L x fSW
where VDS is the voltage drop across the internal MOSFET switch. IL is the peak-to-peak inductor ripple current as calculated above. VQ is the portion of input ripple due to the capacitor discharge, and VESR is the contribution due to ESR of the capacitor.
PSW =
IL 2 IL IPK = IO + 2 VIN x IO x ( tR + tF ) x fSW IDC = IO - 4
Output Capacitor For the boost converter, the output capacitor supplies the load current when the main switch is on. The required output capacitance is high, especially at higher duty cycles. Also, the output capacitor ESR needs to be low enough to minimize the voltage drop due to the ESR while supporting the load current. Use the following equation to calculate the output capacitor for a specified output ripple tolerance:
V ESR = ESR IPK IO x DMAX COUT = VQ x fSW where IPK is the peak inductor current as defined in the following Power Dissipation section, IO is the load current, VQ is the portion of the ripple due to the capacitor discharge, and VESR is the contribution due to the ESR of the capacitor. DMAX is the maximum duty cycle at minimum input voltage.
See the Electrical Characteristics table for the RON(MAX) maximum value. For the boost converter: IRMS =
(I2DC + I2PK + (IDC x IPK )) x DMAX 3
V xI IIN = O O VIN x IL =
(VIN - VDS ) x D
L x fSW
IDC = IIN -
IL 2 IL IPK = IIN + 2
PDC = IRMS2 x RON(MAX) where VDS is the drop across the internal MOSFET and is the efficiency. See the Electrical Characteristics table for the RON(MAX) value. PSW = VO x IIN x (tR + tF ) x fSW 4
Power Dissipation
The MAX5099 includes two internal power MOSFET switches. The DC loss is a function of the RMS current in the switch while the switching loss is a function of switching frequency and instantaneous switch voltage and current. Use the following equations to calculate the RMS current, DC loss, and switching loss of each converter. The MAX5099 is available in a thermally enhanced package and can dissipate up to 2.7W at +70C ambient temperature. The total power dissipation in the package must be limited so that the operating junction temperature does not exceed its absolute maximum rating of +150C at maximum ambient temperature. For the buck converter: IRMS =
(IDC2 + IPK2 + (IDC x IPK )) x DMAX 3
PDC = IRMS2 x RON(MAX)
where tR and tF are rise and fall times of the internal MOSFET. The tR and tF can be measured in the actual application. The supply current in the MAX5099 is dependent on the switching frequency. See the Typical Operating Characteristics to find the supply current of the MAX5099 at a given operating frequency. The power dissipation (PS) in the device due to supply current (ISUPPLY) is calculated using following equation: PS = VINMAX x ISUPPLY The total power dissipation PT in the device is: PT = PDC1 + PDC2 + PSW1 + PSW2 + PS where PDC1 and PDC2 are DC losses in converter 1 and converter 2, respectively. PSW1 and PSW2 are switching losses in converter 1 and converter 2, respectively.
20
______________________________________________________________________________________
Dual, 2.2MHz, Automotive Synchronous Buck Converter with 80V Load-Dump Protection
Calculate the temperature rise of the die using the following equation: TJ = TC x (PT x JC) where JC is the junction-to-case thermal impedance of the package equal to +1.7C/W. Solder the exposed pad of the package to a large copper area to minimize the case-to-ambient thermal impedance. Measure the temperature of the copper area near the device at a worst-case condition of power dissipation, and use +1.7C/W as JC thermal impedance. 2) Select the unity-gain crossover frequency: f fC SW 20 If the fZERO,ESR is lower than fC and close to fLC, use a Type II compensation network where RFCF provides a midband zero fMID,ZERO, and RFCCF provides a highfrequency pole. 3) Calculate modulator gain G M at the crossover frequency. GM = 0.8 VIN ESR x x VOSC ESR + (2 x fC x L OUT ) VOUT
MAX5099
Compensation
The MAX5099 provides an internal transconductance amplifier with its inverting input and its output available for external frequency compensation. The flexibility of external compensation for each converter offers wide selection of output filtering components, especially the output capacitor. For cost-sensitive applications, use high-ESR aluminum electrolytic capacitors; for component size-sensitive applications, use low-ESR tantalum, polymer, or ceramic capacitors at the output. The high switching frequency of the MAX5099 allows the use of ceramic capacitors at the output. Choose all the passive power components that meet the output ripple, component size, and component cost requirements. Choose the small-signal components for the error amplifier to achieve the desired closed-loop bandwidth and phase margin. Use a simple pole-zero pair (Type II) compensation if the output capacitor ESR zero frequency is below the unity-gain crossover frequency (f C). Type III compensation is necessary when the ESR zero frequency is higher than fC or when compensating for a continuous-mode boost converter that has a right-half-plane zero. Use procedure 1 to calculate the compensation network components when fZERO,ESR < fC.
where VOSC is a peak-to-peak ramp amplitude equal to 1V. The transconductance error-amplifier gain is: GE/A = gM x RF The total loop gain at fC should be equal to 1: GM x GE/A = 1 or V (ESR + 2 x fC x LOUT ) x VOUT RF = OSC 0.8 x VIN x gM x ESR 4) Place a zero at or below the LC double-pole: CF = 1 2 x RF x fLC
5) Place a high-frequency pole at fP = 0.5 x fSW. CCF = CF (2 x 0.5fSW x RF x CF ) - 1
Buck Converter Compensation Procedure 1 (See Figure 3) 1) Calculate the f ZERO,ESR and LC double-pole frequencies:
fZERO,ESR = fLC = 1 2 x ESR x COUT 1 2 LOUT x COUT
R2 R1
VOUT
FB_
gM
COMP_
VREF
+ RF CF CCF
Figure 3. Type II Compensation Network
______________________________________________________________________________________ 21
Dual, 2.2MHz, Automotive Synchronous Buck Converter with 80V Load-Dump Protection
Procedure 2 (See Figure 4) If the output capacitor used is a low-ESR ceramic type, the ESR frequency is usually far away from the targeted unity crossover frequency (fC). In this case, Type III compensation is recommended. Type III compensation provides two-pole zero pairs. The locations of the zero and poles should be such that the phase margin peaks around fC. It is also important to place the two zeros at or below the double pole to avoid the conditional stability issue. 1) Select a crossover frequency:
f fSW SW 20 2) Calculate the LC double-pole frequency, fLC: fLC = 1 2 x L OUT x COUT 1 at 0.75 x fLC. 2 x RF x CF 7) Place a second pole at 1/2 the switching frequency. CCF =
MAX5099
VOUT CCF RI CI CF
R1 FB_ R2
RF
gM +
COMP_
VREF
Figure 4. Type III Compensation Network
3) Place a zero fZ1 = where CF =
(2 x 0.5 x fSW x RF x CF ) - 1
CF
1 2 x 0.75 x fLC x RF
and RF 10k. 4) Calculate CI for a target unity crossover frequency, fC. CI = 2 x fC x L OUT x COUT x VOSC VIN x RF
Boost Converter Compensation The boost converter compensation gets complicated due to the presence of a right-half-plane zero fZERO,RHP. The right-half-plane zero causes a drop in phase while adding positive (+1) slope to the gain curve. It is important to drop the gain significantly below unity before the RHP frequency. Use the following procedure to calculate the compensation components:
1) Calculate the LC double-pole frequency, fLC, and the right-half-plane-zero frequency. fLC = 1- D 2 x L OUT x COUT
1 5) Place a pole fP1 = at fZERO,ESR. 2 x RI x CI RI = 1 2 x fZERO,ESR x CI where
fZERO,RHP =
(1 - D)2R(MIN)
2 x L OUT
6) Place a second zero, f Z2 , at 0.2 x f C or at f LC , whichever is lower. R1 = 1 2 x fZ2 x CI
- RI
D = 1- R(MIN) =
VIN VOUT VOUT
IOUT(MAX)
Target the unity-gain crossover frequency for: fC
22
fZERO,RHP 5
______________________________________________________________________________________
Dual, 2.2MHz, Automotive Synchronous Buck Converter with 80V Load-Dump Protection
2) Place a zero fZ1 = 1 at 0.75 x fLC. 2 x RF x CF 1 2 x 0.75 x fLC x RF Choose a suitable power MOSFET that can safely operate in the saturation region. Verify its capability to support the downstream DC-DC converters' input current during the load-dump event by checking its safe operating area (SOA) characteristics. Since the transient peak power dissipation on the MOSFET can be very high during the load-dump event, also refer to the thermal impedance graph given in the data sheet of the power MOSFET to make sure its transient power dissipation is kept within the recommended limits.
MAX5099
CF =
where RF 10k. 3) Calculate CI for a target crossover frequency, fC:
2 VOSC (1 - D) + C2L OCO CI = CRF VIN
Improving Noise Immunity
In applications where the MAX5099 is subject to noisy environments, adjust the controller's compensation to improve the system's noise immunity. In particular, highfrequency noise coupled into the feedback loop causes jittery duty cycles. One solution is to lower the crossover frequency (see the Compensation section).
where C = 2 x fC. 4) Place a pole fP1 = 1 at fZERO,RHP 2 x RI x CI 1 2 x f x CI
or 5 x fC, whichever is lower. RI =
VL
1 at fLC. 5) Place the second zero fZ2 = 2 x R1x CI R1 = 1 2 x fLC x CI
MAX5099
VDRV - RI BST_/VDD_ V+ PGND
6) Place the second pole at 1/2 the switching frequency. CCF =
(2 x 0.5 x fSW x RF x CF ) - 1
DRAIN_ DRAIN_ *DL_ SOURCE_ SOURCE_ SGND FB_ COUT
CF
VOUT_
Load-Dump Protection MOSFET
Select the external MOSFET with an adequate voltage rating, VDSS, to withstand the maximum expected loaddump input voltage. The on-resistance of the MOSFET, RDS(ON), should be low enough to maintain a minimal voltage drop at full load, limiting the power dissipation of the MOSFET. During regular operation, the power dissipated by the MOSFET is: PNORMAL = ILOAD2 x RDS(ON) where ILOAD is equal to the sum of both converters' input currents. The MOSFET operates in a saturation region during load dump, with both high voltage and current applied.
*LEAVE DL_ UNCONNECTED.
Figure 5. Boost Application
______________________________________________________________________________________
23
Dual, 2.2MHz, Automotive Synchronous Buck Converter with 80V Load-Dump Protection MAX5099
PCB Layout Guidelines
Careful PCB layout is critical to achieve low switching losses and clean, stable operation. This is especially true for dual converters where one channel can affect the other. Refer to the MAX5098A/MAX5099 Evaluation Kit data sheet for a specific layout example. Use a multilayer board whenever possible for better noise immunity. Follow these guidelines for good PCB layout: 1) For SGND, use a large copper plane under the IC and solder it to the exposed paddle. To effectively use this copper area as a heat exchanger between the PCB and ambient, expose this copper area on the top and bottom side of the PCB. Do not make a direct connection from the exposed pad copper plane to SGND underneath the IC. 2) Isolate the power components and high-current path from the sensitive analog circuitry. 3) Keep the high-current paths short, especially at the ground terminals. This practice is essential for stable, jitter-free operation. 4) Connect SGND and PGND together at a single point. Do not connect them together anywhere else (refer to the MAX5099 Evaluation Kit data sheet for more information). 5) Keep the power traces and load connections short. This practice is essential for high efficiency. Use thick copper PCBs (2oz vs. 1oz) to enhance fullload efficiency. 6) Ensure that the feedback connection to COUT is short and direct. 7) Route high-speed switching nodes (BST_/VDD_, SOURCE_) away from the sensitive analog areas (BYPASS, COMP_, and FB_). Use the internal PCB layer for SGND as an EMI shield to keep radiated noise away from the IC, feedback dividers, and analog bypass capacitors.
Layout Procedure
1) Place the power components first, with ground terminals adjacent (inductor, CIN_, and COUT_). Make all these connections on the top layer with wide, copper-filled areas (2oz copper recommended). 2) Group the gate-drive components (bootstrap diodes and capacitors, and VL bypass capacitor) together near the controller IC. 3) Make the DC-DC controller ground connections as follows: a) Create a signal ground plane underneath the IC. b) Connect this plane to SGND and use this plane for the ground connection for the reference (BYPASS), enable, compensation components, feedback dividers, and OSC resistor. c) Connect SGND and PGND together (this is the only connection between SGND and PGND). Refer to the MAX5098A/MAX5099 Evaluation Kit data sheet for more information.
24
______________________________________________________________________________________
GATE
V+
DRAIN1 DRAIN1
IN_HIGH
ON/OFF
DRAIN2 DRAIN2
VDRV
1 2 R12 C11 JU4 8 16 15
OSC
BYPASS
SGND
27
VIN
Dual, 2.2MHz, Automotive Synchronous Buck Converter with 80V Load-Dump Protection
MAX5099
______________________________________________________________________________________
VIN = 4.5V TO 5.5V PGND C1 VIN C19 C4 22 23 D4 31 C14 25 SOURCE1 24 SOURCE1 SOURCE2 SOURCE2 30 3 29 6 FB2 R18 COMP2 7 C17 R16 32 D5 N2 DL1 DL2 4 19 FB1 C9 R9 18 COMP1 R7 3 28 1 L2 1256 N3 4 R15 R23 C16 C5 VOUT2 PGND 23 VDRV VDRV 12 11 10 13 D1 26 BST1/VDD1 C6 BST2/VDD2 C15 D2 6521
C12
VL
Figure 6. 4.5V to 5.5V Operation
MAX5099
PGND R17 C20 21 PGOOD1 EN1 R11 17 FSEL_1 20 VL EN2 SYNC 9 PGOOD2 4 5 C21 SGND 14 C13
VOUT1
L1
PGND
C7
R6
R22
C8
R8
SGND
25
MAX5099
GATE
V+
DRAIN1 DRAIN1
IN_HIGH
ON/OFF
DRAIN2 DRAIN2
OSC
BYPASS
SGND
VDRV
1 2 JU4 R12 6.49 C11 0.22F VDRV
8 16 15
27 R21 1 C12 2.2F
VL
Dual, 2.2MHz, Automotive Synchronous Buck Converter with 80V Load-Dump Protection
26
N1 VIN = 5.2V TO 19V PGND C19 1F 25V C4 10F 25V C15 10F 25V 23 D4 31 C14 0.1F L2 4.7H D5 C5 22F VDRV 22 23 10 13 C1 22F 100V R1 3.9k C2 4.7F 35V VDRV 12 11 D1 26 BST1/VDD1 L1 4.7H 25 SOURCE1 24 SOURCE1 SOURCE2 SOURCE2 32 3 4 29 6 C17 R18 7.15 2700pF 1256 N3 32 N2 DL1 DL2 4 19 C9 R9 2700pF 12.7 18 COMP1 COMP2 7 FB1 FB2 R7 10k 1% C20 33pF 21 PGOOD1 EN1 VL R11 17 FSEL_1 20 EN2 SYNC 14 VL C13 4.7F 3 28 1 D2 6521 C6 0.1F BST2/VDD2 C3 150F 25V VIN VOUT2 PGND VOUT2 = 3.3V AT 1A
VOUT1 = 5V AT 2A
VOUT1
PGND
C7 22F
R6 52.3k 1%
MAX5099
PGND
R15 37.4k 1% R23 10k 1% R16 12.1k 1% C21 56pF C16 270pF R17 976 1%
R22 10k 1%
C8 270pF
R8 976 1%
PGOOD2
4 5 9
______________________________________________________________________________________
Typical Application Circuit
SGND
SGND
Dual, 2.2MHz, Automotive Synchronous Buck Converter with 80V Load-Dump Protection MAX5099
Pin Configuration
PROCESS: BiCMOS
TOP VIEW
SOURCE1 PGOOD1 DRAIN1 DRAIN1 COMP1 FSEL_1 EN1 FB1
Chip Information
24 SOURCE1 25 BST1/VDD1 26 VDRV 27 DL1 28 PGND 29 DL2 30 BST2/VDD2 31 SOURCE2 32 1 SOURCE2
23
22
21
20
19
18
17 16 15 14 13 BYPASS SGND VL V+ IN_HIGH ON/OFF GATE SYNC
Package Information
For the latest package outline information, go to www.maxim-ic.com/packages. PACKAGE TYPE 32 TQFN PACKAGE CODE T3255+4 DOCUMENT NO. 21-0140
MAX5099
12 11
+
2 DRAIN2
*EP
10 9
3 DRAIN2
4 PGOOD2
5 EN2
6 FB2
7 COMP2
8 OSC
TQFN (5mm x 5mm)
*CONNECT EXPOSED PAD TO GROUND PLANE AND TO SGND.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 27
(c) 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

▲Up To Search▲

Price & Availability of MAX5099

	To Download MAX5099 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .